Nature16d
Current Mode Analog Multipliers and Dividers in CMOS Technology
Another notable contribution is the design of a four-quadrant analog multiplier using dynamic threshold voltage MOSFET (DTMOS) technology. This circuit achieves low power consumption and a wide ...
Design-Reuse5y
Low Power Clock Multiplier PLL for 40nm TSMC ULP CMOS
The OT3135 is a flexible low power clock multiplier PLL function with a wide range of input and output frequencies, and is designed for TSMC 40nm, ULP CMOS processes.